Digital signal processing (DSP) can be used to manipulate data signals to modify or improve those signals. FIG. 1 illustrates an example of a prior art DSP circuit 100 that receives an input digital signal sample stream 102 of digital signal samples of a single data signal and feeds the input digital signal sample stream 102 into a DSP Module 116 to be processed in accordance with a DSP algorithm. As shown, the input digital signal sample stream 102 is first input into a delay D0 104. After a delay, the digital signal samples of the input digital signal sample stream 102 are output from the delay D0 104, as a delay output 106. Delay output 106 is then input into a second delay D1 108. As shown, a delay chain of “m” number of delays is created with the delay output of each delay of the delay chain being connected to an input of subsequent delay, which is continued to delay Dm 112. Delays D0 104, D1 108, . . . Dm 112 are each configured to delay a single digital signal sample for a preconfigured time. Thus, each delay D0 104, D1 108, . . . Dm 112 delays a digital signal sample from the input digital signal sample stream 102 for a predetermined time, until it is passed to a subsequent delay and/or to the DSP module 116.
As further shown in FIG. 1, the input digital signal sample stream 102 and the delay output 106, 110, 114 of each delay D0 104, D1 108, . . . Dm 112 are input into the DSP module 116. These inputs thus provide the DSP module 116 with a sequence of m+1 digital signal samples from the input digital signal sample stream 102, with “m” being the number of delays. Such a sequence may be used in various DSP algorithms of a DSP module 116, including but not limited to a finite impulse response (FIR) filter, an infinite impulse response filter (IIR), an equalizer, a numerically controlled oscillator (NCO), and the like.
While the illustrated DSP circuit 100 can effectively process an input digital signal sample stream 102 of a single signal, challenges arise when multiple signals need to be processed. Traditionally, one solution has been to duplicate the DSP circuit 100 for each input signal. This solution, however, is hardware intensive since it requires multiple instantiations of the same DSP circuit 100. Another solution has been to buffer each signal and process them serially in the same DSP circuit 100. While this solution does not require the duplication of hardware, it can significantly slow down the DSP processes. Accordingly, the present invention provides a DSP apparatus that is capable of timely processing multiple signals in a single instantiation of a DSP apparatus.